IEEE

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

Abstract: The major challenge faced by modern compute-in-memory (CIM) designs is that they rely heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and ...
IEEE

Ternary Output Binary Neural Network With Zero-Skipping for MRAM-Based Digital In-Memory Computing

Abstract: This brief presents a novel ternary output binary neural network (BNN) and an MRAM-based digital in-memory computing (IMC) architecture. The proposed ternary output BNN and IMC architecture ...