IEEE

Design of Adder Circuits using GNRFETs in Ternary Logic

Abstract: This paper presents the design of ternary adder schematics with graphene nanoribbon field effect transistor (GNRFET). The adder circuits are developed by using the basic, universal and ...
EurekAlert!

AI points toward a new paradigm for fully automated processor chip design

A Perspective in National Science Review outlines a new paradigm for fully automated processor chip design. By combining ...
IEEE

Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs

Abstract: The application of artificial intelligence (AI) requires advanced computation to address complex problems. However, the improvement of binary computing systems supporting these applications ...
Hackaday

Unusual Circuits In The Intel 386’s Standard Cell Logic

Intel’s 386 CPU is notable for being its first x86 CPU to use so-called standard cell logic, which swapped the taping out of individual transistors with wiring up standardized functional blocks. This ...