Write a Verilog code for a 3 to 8 decoder using a 2 to 4 decoder and show the simulation on Quartus II. wo W1 wo W1 yo y1 y2 y3 yo y1 y2 y3 W2 En En wo W1 yo y1 y2 y3 y4 y5 y6 y7 En
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